1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and particularly to a nonvolatile semiconductor memory device called a flash memory and including memory cells each formed of one floating gate field effect transistor. More particularly, the invention relates to a structure for stably reading data even if a threshold voltage of the memory cell transistor is low.
2. Description of the Background Art
A memory called a flash memory has been known as one of memories which store information in a nonvolatile manner. In this flash memory, each memory cell is formed of one floating gate field effect transistor. Storage of data is performed by injection/ejection of electrons with respect to a floating gate. In an N-channel MOS transistor, a threshold voltage Vth of a floating gate field effect transistor (memory cell transistor) increases when electrons are injected into the floating gate, and the threshold voltage Vth of the memory cell transistor lowers when electrons are drawn out or ejected from the floating gate. The floating gate is electrically isolated from other portions by an insulating film, and continuously holds electrons. The high and low states of threshold voltages Vth, which are set in accordance with the quantity of electric charges in the floating gate as described above, are correlated to "1" and "0" of binary information.
In reading data, a voltage intermediate the high and low threshold voltages is applied to a control electrode, and data reading is performed by determining whether a current flows through the memory cell transistor or not.
In a nonvolatile semiconductor memory device, the memory cells are arranged in rows and columns, and word lines are arranged corresponding to the respective rows. Also, bit lines are arranged corresponding to the respective columns. Lowering of the threshold voltage is performed on a predetermined number of memory cells at a time. If there are variations in write/erase characteristics of the memory cells, which exhibit the degrees of injection and ejection of electrons into and from the floating gates, a threshold voltage Vth of a certain memory cell may be excessively low and close to 0 V, and a leak current in this memory cell may increase. In an NOR type flash memory, this state in which the threshold voltage is low and close to or below 0 V is called an "over-erased" state. The NOR type flash memory is a memory having a structure in which all memory cells in each column are connected to the same bit line. In a DINOR type flash memory, the state in which the threshold voltage is excessively low is called an "over-programmed" state. In the DINOR type flash memory, a plurality of sub-bit lines are arranged for the memory cells in each column, and the sub-bit lines connected to the memory cells are connected to a main bit line through select transistors, respectively.
If such an over-erased or over-programmed memory cell exists, memory cell data cannot be precisely read out due to the leak current thereof. In the following description, the over-erased state of the NOR type flash memory and the over-programmed state of the DINOR type flash memory may be genericly referred to as an "over-low Vth" state. For preventing an influence by the memory cell in the over-low Vth state, such a structure has been proposed in which memory cell current flows only through memory cells of two bits at most in a selected column.
FIG. 78 schematically shows a structure of an array of a conventional NOR type flash memory. FIG. 78 shows memory cells MT arranged in four rows and three columns. Each memory cell MT is formed of one floating gate field effect transistor. Word lines WLa, WLb, WLc and WLd are arranged corresponding to the respective rows of memory cells MT, and bit lines BLa, BLb and BLc are arranged corresponding to the respective columns of memory cells MT. A sub-source line SSLa is arranged for memory cells MT connected to a set of word lines WLa and WLb adjacent to each other, and a sub-source line SSLb is arranged for memory cells MT connected to another set of word lines WLc and WLd adjacent to each other. Source line select transistors SSTa-SSTd, which are turned on in response to signal potentials on corresponding word lines WLa-WLd, are arranged in the corresponding rows of memory cells MT, respectively. When turned on, these source line select transistors SSTa-SSTd connect a main source line MSL to sub-source lines SSLa or SSLb arranged for the corresponding row. Main source line MSL is connected to sub-source line SSLa and SSLb through diodes Da and Db, respectively.
For reading data, a voltage of about 5 V is applied to a selected word line, and a read voltage of about 1 V is applied to a selected bit line. Also, a voltage of 0 V is applied to main source line MSL. It is now assumed that data is to be read from memory cell MT arranged at the crossing between word line WLa and bit line BLa. In this case, source line select transistor SSTa is turned on in accordance with the signal voltage on word line WLa to electrically connect main source line MSL to sub-source line SSLa. The voltages on unselected word lines WLb-WLd are 0 V, and source line select transistors SSTb-SSTd keep the off state. Therefore, sub-source line SSLb is in an electrically floating state and current paths of the memory cells connected to corresponding word lines WLc and WLd are cut off.
A sense amplifier (not shown) determines whether a current flows through bit line BLa or not. Even if memory cell MT arranged at the crossing between word line WLb and bit line BLa is in the over-low Vth state, the leak current thereof is extremely small, and data can be accurately read from the selected memory cell. Thus, only an influence of the memory cell in the over-low Vth state of one bit at the maximum appears on the selected bit line in the data read operation so that the leak current can be sufficiently small, and data reading can be accurately performed. Even if threshold voltage Vth is negative and the leak current is large, a failure occurs only in one bit, and an error detection and correction circuit can correct such a failure.
Description will now be given on a programming operation for memory cell MT arranged corresponding to the crossing between word line WLa and bit line BLa. In the programming operation, the threshold voltage of memory cell MT is increased. In this case, a voltage of about 12 V is applied to word line WLa, a voltage of about 6 V is applied to bit line BLa, and a voltage of 0 V is applied to main source line MSL. Source line select transistor SSTa is turned on to transmit the ground voltage of 0 V to sub-source line SSLa. Thereby, hot electrons are generated in the selected memory cell MT as a result of avalanche breakdown caused by a high electric field near the drain, and these hot electrons are injected into the floating gate. Unselected bit lines BLb and BLc as well as unselected word lines WLb-WLd are held at the ground voltage level, and source line select transistors SSTb-SSTd are off.
For an erase mode, i.e., when threshold voltage Vth of memory cell MT is to be lowered, a voltage of 0 V is applied to word lines WLa-WLd, a voltage of about 12 V is applied to main source line MSL, and all bit lines BLa-BLc are set to an open state. The high voltage of 12 V on main source line MSL is transmitted to sub-source lines SSLa and SSLb through diodes Da and Db, respectively. Thereby, a high electric field is applied between the floating gate and the source in each memory cell MT, and electrons are moved from the floating gate to the source by a Fowler-Nordheim (FN) tunneling phenomenon. In the erase mode, all word lines WLa-WLd are held at the ground voltage level so that source line select transistors SSTa-SSTd maintain the off state. Therefore, diode elements Da and Db are required for applying a high voltage to the sources of memory cells MT.
In the flash memory, e.g., shown in FIG. 78, each sub-source line is commonly used only by the adjacent two word lines. In reading of data, therefore, each bit line is affected only by the leak current of the over-erased memory cell of one bit at the maximum, and erroneous reading of data due to the over-erased memory cell can be prevented. In the structure shown in FIG. 78, however, it is necessary to provide diodes D (Da and Db) for sub-source lines SSL (SSLa and SSLb), respectively. Accordingly, the pitch of the word lines depends on the size of diodes Da and Db, and therefore cannot be reduced so that high-density integration is difficult.
A structure in which the diodes are removed for reducing the word line pitch has been disclosed, e.g., in Japanese Patent Laying-Open No. 6-275083 (1994).
FIG. 79 schematically shows a structure of a memory array disclosed in the above reference. In FIG. 79, portions corresponding to those in FIG. 78 bear the same reference numerals, and will not be specifically described below. As shown in FIG. 79, sub-source line SSLa is connected to main source line MSL through source line select transistor SSTa and SSTb, and sub-source line SSLb is connected to main source line MSL through source line select transistors SSTc and SSTd.
In the data read operation of the arrangement shown in FIG. 79, voltages are applied in the same manner as in the memory shown in FIG. 78. However, in the programming mode requiring an increase of the threshold voltage, voltages are applied as indicated inside the parentheses. FIG. 79 shows voltages applied to word lines WLa and bit line BLa for writing data into the memory cell.
Thus, word line WLa is set to 12 V, and unselected word lines WLb-WLd are set to the ground voltage level of 0 V. Selected bit line BLa is set at a voltage of 0 V or 6 V depending on the write data, and unselected bit lines BLb and BLc are set to the open state. Main source line MSL is at a voltage of 6 V. In this state, therefore, a voltage of 6 V is transmitted onto sub-source line SSLa through source line select transistor SSTa. The voltage of 0 V or 6 V transmitted onto the selected bit line BLa is selected in accordance with "0" or "1" of write data. When the voltage on bit line BLa is set to 0 V, a channel current flows from sub-source line SSLa to bit line BLa through memory cell MT arranged corresponding to the crossing between bit line BLa and word line WLa. Thereby, a high electric field occurs in the impurity region (source region) connected to sub-source line SSLa, and channel hot electrons are produced as a result of avalanche breakdown caused by this high electric field so that electrons are injected into the floating gate.
When the voltage on bit line BLa is set to 6 V, the source and drain voltages of memory cell MT are equal to each other so that a channel current does not flow, and injection of electrons into the floating gate does not occur. In this state, therefore, the erased state is maintained. In the foregoing arrangement, however, word line WLa is at a high voltage of 12 V. Therefore, the memory cell transistors connected to bit lines BLb and BLc are turned on so that the voltage of 6 V is transmitted to bit lines BLb and BLc from sub-source line SSLa. Accordingly, a voltage of 6 V is transmitted to impurity regions (drain regions), which are connected to the bit lines, in the memory cells connected to unselected word lines WLb and WLd, and a stress called a "disturb stress" is applied. As a result of the bit line voltages of these unselected memory cells, a quantity of electric charges in the floating gates changes due to ejection of electrons caused by the Fowler-Nordheim tunneling current or due to injection of holes into the floating gates caused by interband tunneling currents, resulting in a problem that the threshold voltages change.
In this case, data may be simultaneously written into all the memory cells in one row. In the data write operation, however, a large current, such as hundreds of microamperes per cell flows at the time of injection of hot electrons produced by drain avalanche and at the time of injection of electrons into the floating gate from the channel region caused by channel hot electrons. Therefore, it is usually difficult to effect writing simultaneously on all the memory cells in one row.
In the erase mode, as shown in FIG. 80, all word lines WLa-WLd are set to the ground voltage level of 0 V. A voltage of about 10 V is applied to selected bit line BLa, and unselected bit lines BLb and BLc are set to the open state. In this state, all source line select transistors SSTa-SSTd are off, and sub-source lines SSLa and SSLb are set to the open state. In this state, a large voltage is applied between the floating gate and the drain in each memory cell MT connected to bit line BLa, and electrons are ejected from the floating gate by the Fowler-Nordheim current caused by the high electric field applied between the floating gate and the drain region. In this case, therefore, data in all memory cells MT connected to bit line BLa is erased. According to the structure in which one word line is selected and writing is performed simultaneously for multiple bits, data of the cell to be held is also erased so that it is impossible to employ this scheme of performing the erasing on a row at a time.
In the structure shown in FIGS. 79 and 80, the source and drain regions have their functions merely inverted from those of the conventional flash memory in programming and erase operations. Even in this structure, the drain disturb stress is applied not only to the memory cells in the same column as that of the selected memory cell but also to the memory cells in the unselected columns during writing, and therefore data cannot be held stably.
The foregoing problem of over-erasing occurs as over-programming in a DINOR type flash memory shown in FIG. 81.
FIG. 81 schematically shows a structure of a main portion of a conventional DINOR type flash memory. FIG. 81 representatively shows two sub-bit lines SBLa and SBLb connected to one main bit line MBL. A plurality of sub-bit lines SBL in the column direction are also connected to main bit line MBL. Memory cells MT are arranged corresponding to crossings between sub-bit lines SBLa and SBLb and word lines WLa and WLb. Each memory cell MT is formed of a floating gate field effect transistor. Sub-bit lines SBLa and SBLb are connected to main bit line MBL through sector select gates SGa and SGb, respectively. Sector select gates SGa and SGb are turned on in response to activation of sector select signals .phi.SA and .phi.SB.
In this DINOR type flash memory, memory cells MT are not connected to main bit line MBL, but are connected only to sub-bit lines SBLa and SBLb. Therefore, a load capacitance of the bit line is small during data reading, and data can be read fast.
In the programming operation, a voltage of about -8 V is applied to a selected word line, a voltage of about 6 V is applied to a selected sub-bit line, and the ground voltage of 0 V is applied to unselected word lines. The unselected sub-bit lines are held in the floating state. In this state, a voltage of 0 V or 6 V depending on the write data is applied to the selected sub-bit line. In the memory cells connected to the sub-bit line at the voltage of 6 V, electrons are ejected from the floating gates through Fowler-Nordheim tunneling current so that the threshold voltages thereof lower.
In the erase mode, a voltage of about 10 V is applied to the selected word line, and a voltage of about -8 V is applied to the back gates of the memory cells MT and sub-source line SSL. Electrons are injected into the floating gate through the Fowler-Nordheim tunneling current flowing from the whole surface of the channel in each selected memory cell transistor, and threshold voltage Vth of the memory cell is increased.
In this DINOR type flash memory, the memory cells connected to a sub-bit line are smaller in number than those in the NOR type flash memory, but a large number of memory cells are coupled to each sub-bit line so that data cannot be read out accurately due to a leak current if an over-programmed memory cell is present.